1. Field of the Invention
The present invention relates generally to semiconductor devices, and particularly to a semiconductor device having a dummy pattern which functions as a pattern for preventing an element formation region from being polished in the process of chemical-mechanical polishing an isolation insulating film.
2. Description of the Background Art
In order to avoid a problem which arises in a CMP (Chemical Mechanical Polishing) process that the flatness of an isolation insulating film in an element isolation region is degraded due to nonuniformity in density of patterns of element formation regions to be produced, a semiconductor device having a dummy pattern arranged in the element isolation region has conventionally been produced. Japanese Patent Laying-Open No 8-213396, for example, discloses an example of the dummy pattern in an interconnect layer, and Japanese Patent Laying-Open No. 9-181159 discloses an example of the dummy pattern used when STI (Shallow Trench Isolation) scheme is employed for isolating an element formation region pattern.
In the semiconductor devices of recent years, all elements are isolated from each other according to STI for simplification of the manufacturing process. Referring to FIG. 17, the region where an element formation region pattern 104 is not produced, that is, an element isolation region 103 thus occupies a considerably large area relative to element formation region pattern 104. In such a state, if a film 102 which becomes an isolation insulating film is deposited on a semiconductor substrate 101 and CMP is applied thereto, the finally produced surface of an isolation insulating film 102a formed in a large element isolation region 103a has an appreciably large depression as shown in FIG. 18, compared with an isolation insulating film 102b formed in a small element isolation region 103b. A scheme devised for preventing such a large depression in the surface of the isolation insulating film is to provide a dummy pattern 105 in large element isolation region 103a before depositing film 102 which becomes the isolation insulating film, and then carry out CMP as shown in FIG. 19. According to this scheme, the surface of isolation insulating film 102a left in large element isolation region 103a does not have such a large depression after CMP as shown in FIG. 20. As a result, in the state shown in FIG. 20 generated by providing dummy pattern 105 and then performing CMP, the flatness of the surface of isolation insulating film 102a formed in large element isolation region 103a is improved compared with the state of FIG. 18 generated by performing CMP without forming dummy pattern 105.
Even if the dummy pattern is formed in the element isolation region as described above, the improvement above may not be accomplished when the ratio of a two-dimensional area occupied by protruded element formation region patterns to the entire semiconductor chip region, that is, density of the element formation region patterns in the surface, and the ratio of a two-dimensional area occupied by protruded dummy patterns, that is, density of the dummy patterns in the surface considerably vary depending on the part of the entire semiconductor chip. In this case, the partial difference between the ratio of the area occupied by the element formation region patterns and that occupied by the dummy patterns could lead to difference in polishing rate by a CMP polishing cloth depending on respective parts of the chip. For example, if dummy patterns which occupy a small area and thus cause a high polishing rate are arranged, the region where such dummy patterns are provided is excessively polished. This is because the thickness of the remaining insulating film after polishing is determined according to the ratio of the area occupied by the element formation region patterns and that occupied by the dummy patterns if the polishing time is the same as shown in FIG. 21. Particularly, if the ratio of the area occupied by the element formation region patterns and that occupied by the dummy patterns are different by 20% in each part of the semiconductor substrate, a step of significance (significant step) of at least 500 .ANG. is generated in the isolation insulating film after polishing. Such a significant step could considerably degrade the size controllability of the gate electrode or the like fabricated in a process after CMP.
A method for avoiding generation of the significant step is to set the proportion of the ratio of the area occupied by the element formation region patterns to that occupied by the dummy patterns at a predetermined value.
However, even if the proportion of the ratio of the area occupied by the element formation region patterns to that by the dummy patterns is set at a predetermined value, no consideration is given to the difference of the deposited state of the insulating film caused by the difference of the method of depositing the insulating film on the element formation region patterns and dummy patterns. Therefore, the flatness of the insulating film after CMP could partially be different depending on the deposition method of the insulating film.
In the manufacturing process of the semiconductor device, after the element isolation insulating film is formed by providing the dummy pattern and then performing CMP, a step of forming a gate electrode which connects the element formation region patterns to each other and a step of injecting impurities into the element formation region patterns are required. In these process steps, if the gate electrode is formed in contact with a dummy pattern having impurities, the dummy pattern electrically influenced by the gate electrode could electrically influence the element formation region patterns.
Further, if a dummy pattern is formed in an impurity diffusion region such as the region on the boundary between wells and an interconnect layer passes over the boundary, an unfavorable phenomenon of latchup could occur at the boundary of the wells.
A mask should be prepared such that dummy patterns are arranged by taking into consideration all the various conditions as discussed above. There is accordingly a demand for introduction of a technique of automatically determining the arrangement of dummy patterns by the CAD process to facilitate designing.